The proposed Double Edge Triggered Flip Flop will double the frequency of data transfer for the same input clock cycle (or halve the input clock signal’s frequency for the same data transfer rate), while working on comparatively similar voltages and dissipating comparatively similar power, hereby regulating the power dissipated in a circuit. Therefore, reducing the power dissipated due to clock and logic gates would definitely reduce the net power dissipated in a circuit. (3) Power dissipated in the logic gate that is driving the data input of the Flip Flop. (2) Power dissipated in the clock buffer that is driving the clock input of the Flip Flop. Now, there are mainly three components of power dissipation in a Flip Flop :- (1) Power consumed by internal and input nodes during the latching operations including the power dissipated driving the output load. Also, Edge Triggered Flip Flops are popularly used in modern VLSI designs and contribute majorly in the net power consumption by the circuit. The complexity in a circuit design can be reduced by using synchronous clock inputs instead of an asynchronous one. Hence, this approach wouldn’t not provide much benefits. But voltage scaling would definitely affect the scaling of threshold voltage, which may cause the leakage power to rise exponentially. Power Consumption is affected by many factors leaving other design and frequency factors aside, however, it can be related as directly proportional to the square of the voltage supply. This, however, can be avoided if a new design is incorporated, one which would be consuming comparatively less power while maintaining comparable performance. Normally, the circuits which display high performance and usually have a very complex structure as well as a dense integration, require a high clock frequency for faster operation, which in turn consumes power. The restricted input of S-R latch toggles the output of JK flip-flop.In the past, the VLSI ( Very Large Scale Integration ) designers were concerned and focused mainly on smaller silicon area, performance (higher calculation speed), cost and reliability where as power considerations were given a secondary importance but due to huge increase in the demand, popularity and the number of users of the mobile devices (portable electronics) in the modern society, the primary concern of the VLSI designers has now been shifted to Power efficiency and Energy savings. JK flip-flop is same as S-R flip-flop but without any restricted input. When En = 0, the flip-flop will retains its state & when En = 1, it can change its state upon next clock cycle. It does not matter if there is a clock edge, the flip-flop will hold its state if it is disabled. D Flip-Flop with EnableĮnable pin enables the D flip-flop to hold its last state without considering the clock signal. S,R state does not go to hold state until the clock signal = 0. Thus this flip-flop works on positive or rising edge of the clock signal. Both inputs to the gate 4 are high, so the output of gate 4 R = 0.it will reset the output state Q = 0. Now if clk = 0 the S,R = 1 & the flip-flop will hold the current state.Īgain when clk = 1 and D = 0. R = 1, S = 0 will set the output state Q = 1. That makes the output of gate 2 S = 0 because both inputs are high. One input of gate 1 is low so its output = 1. One input of gate 3 is low “0”, so its output = 1, which is R = 1. When clk = 1 and D =1 then gate 4 output = 0 because R = 1. When clk = 0, then S = 1 and R = 1, which is hold state for NAND gate SR latch.
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